The present invention relates to electronic circuits, and more particularly, to techniques for providing calibrated parallel on-chip termination impedance on integrated circuits.
Signal reflection can occur on transmission lines when there is a mismatch between the characteristic impedance of the transmission line and the impedance of the transmitter and/or receiver. The reflected signal can interfere with the transmitted signal, causing distortion and degrading signal integrity.
To solve this problem, transmission lines are resistively terminated by a matching impedance to minimize or eliminate signal reflection. Input/output (I/O) pins on an integrated circuit package are often terminated by coupling external termination resistors to the appropriate I/O pins. However, many integrated circuit packages require a large number of termination resistors, because they have a large number of I/O pins. Therefore, it is becoming more common to resistively terminate transmission lines using on-chip termination (OCT) circuits to reduce the number of external components and to conserve board area.
Un-calibrated on-chip termination circuits can have tolerances in the range of +/−30% of a nominal value. In order to improve the accuracy of an on-chip termination (OCT) circuit, a calibration circuit can be used to calibrate the on-chip termination circuit using an off-chip resistor as a reference value.
Many prior art calibration circuits calibrate series on-chip termination impedance for output buffers. However, these calibration circuits typically to do provide accurate parallel on-chip termination impedance for input buffers. In some application, a higher degree of accuracy is required for parallel termination impedance. Therefore, it would be desirable to provide techniques for calibrating parallel on-chip termination impedance circuits to provide more accurate impedance values.